View ST1S50_8140497.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this is information on a product in full production. july 2014 docid025723 rev 3 1/29 ST1S50 4 a monolithic synchronous step-d own switching converter with high efficiency at light load datasheet - production data features ? 4 a output current ? 4.0 v to 18 v input voltage ? output voltage adjustable from 0.8 v to 0.88 x v in ? 500 khz switching frequency ? high efficiency at light load ? programmable soft-start and enable ? integrated 95 m ? and 69 m ? power mosfets ? all ceramic capacitor ? power good ? cycle-by-cycle current limiting ? short-circuit protection ? vfdfpn8 3 x 3 x 1 mm - 10 l applications ? point of load for: stb, tvs, gateway ? solid state disk drive, blu-ray, dvd ?? p/asic/dsp/fpga core and i/o supplies description the ST1S50 device is a 500 khz fixed frequency pwm synchronous step-down regulator. the ST1S50 operates from 4.0 v to 18 v input, while it regulates an output voltage as low as 0.8 v and up to 0.88 x v in . the ST1S50 device integrates a 95 m ? high-side switch and a 69 m ? synchronous rectifier allowing very high efficiency with very low output voltages. the peak current mode control with a special pfm mode enables high efficiency at a light load. the ST1S50 device is available in a vfdfpn8 3 x 3 x 1 mm - 10 leads package. figure 1. application circuit vfdfpn8 vinsw sw fb pg gnda en_ss ST1S50 css cout l r1 r2 cinsw r3 vout vin gndp bst cbst vina comp cc rc cina www.st.com
contents ST1S50 2/29 docid025723 rev 3 contents 1 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 programmable soft-start and enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 error amplifier and control loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.3 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4 power good function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.5 hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.4 compensation network selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5 soft-start capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5.1 reset time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5.2 css value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.6 thermal dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.7 layout consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.8 demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
docid025723 rev 3 3/29 ST1S50 contents 29 9 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
pin settings ST1S50 4/29 docid025723 rev 3 1 pin settings 1.1 pin connection figure 2. pin connection (top view) 1.2 pin description gndp vinsw vina gnda fb sw bst pg en_ss comp ST1S50pur 1 2 3 4 5 10 9 8 7 6 table 1. pin description no. type description 1 gndp power ground. this pin has to be connected to the exposed pad of the device as shown in figure 11: pcb layout on page 22 . 2 vinsw power input voltage 3 vina input voltage 4 gnda ground. this pin has to be connected to the exposed pad of the device as shown in figure 11: pcb layout . 5fb feedback input. connecting the output voltage directly to this pin the output voltage is regulated at 0.8 v. to have higher regulated voltages an external resistor divider is required from the v out to the fb pin. 6comp error amplifier output; the rc network connected to this pin stabilizes the loop. 7en_ss enable and soft-start pin: the capacitor connected to this pin programmes the soft-start time. 8 pg power good pin 9 bst bootstrap pin: the capacitor connected between sw and bst allows the proper high-side switch turn on. 10 sw output switching pin.
docid025723 rev 3 5/29 ST1S50 maximum ratings 29 2 maximum ratings 3 thermal data table 2. absolute maximum ratings symbol parameter value unit v insw power input voltage -0.3 to 20 v v ina input voltage v insw +/- 0.3 v comp , v en_ss , v fb analog pin -0.3 to 3 v sw output switching voltage -1 to v in v pg power good -0.3 to v ina + 0.3 v vbst bootstrap pin (t j from -25 c to 150 c) -0.3 to 22 bootstrap pin (t j from -40 c to -25 c) -0.3 to 21 i fb fb current -1 to +1 ma p tot power dissipation at t a < 60 c 1.5 w t op operating junction temperature range -40 to 150 c t stg storage temperature range -55 to 150 c table 3. thermal data symbol parameter value unit r thja maximum thermal resistance junction ambient (1) 1. package mounted on the demonstration board. vfdfpn8 60 c/w
electrical characteristics ST1S50 6/29 docid025723 rev 3 4 electrical characteristics t j = 25 c, v cc = 12 v, unless otherwise specified. table 4. electrical characteristics symbol parameter test condition values unit min. typ. max. v in operating input voltage range (1) 418 v (2) 417 v inon turn on v in threshold 3.5 v inoff turn off v in threshold 3.0 r dson -hs high-side switch on resistance i sw = 750 ma 95 m ? r dson -ls low-side switch on resistance i sw = 750 ma 69 m ? i lim maximum limiting current (3) 5.6 a oscillator f sw switching frequency 400 500 600 khz d max maximum duty cycle (3) 88 % dynamic characteristics v fb feedback voltage 0.784 0.8 0.816 v (4) 0.776 0.8 0.824 error amplifier gm trans-conductance (3) 250 ? s r o output resistance (3) 240 m ? dc characteristics i q quiescent current duty cycle = 0, no load v fb = 1.2 v 500 600 ? a i qst-by total standby quiescent current off 10 ? a i fb fb bias current 100 na enable v en en threshold voltage device on level 0.340 v device off level 0.130 power good pg pg threshold 91 % v fb pg threshold hysteresis 90 mv pg output voltage low isink = 6 ma open drain 400 mv
docid025723 rev 3 7/29 ST1S50 electrical characteristics 29 soft-start i ss soft-start current v ss = 0.2 v 150 350 550 na v ss = 1 v 4.4 5.4 6.4 ? a v ss = 2 v 0.5 ma protections (3) t shdn thermal shutdown 150 c hysteresis 15 v ff2 fb threshold voltage enabling the short-circuit protection 0.3 v v ff1 fb threshold voltage enabling the f sw /2 0.734 v ovp overvoltage threshold on fb 880 mv hysteresis 80 1. specification referred to t j from -25 to +125 c. 2. specification referred to t j from -40 to -25 c. 3. guaranteed by design. 4. specification referred to t j from -40 to +125 c. specification in the -40 to +125 c temperature range are assured by design, characterization and statistical correlation. table 4. electrical ch aracteristics (continued) symbol parameter test condition values unit min. typ. max.
functional description ST1S50 8/29 docid025723 rev 3 5 functional description the ST1S50 device is based on a ?peak curren t mode?, constant frequency control. the output voltage v out is sensed by the feedback pin (fb) compared to an internal reference (0.8 v) providing an error signal that, compared to the output of the current sense amplifier, controls the on and off time of the power switches. the main internal blocks are shown in the block diagram in figure 3 . they are: ? a fully integrated osc illator that provides th e internal clock and th e ramp for the slope compensation avoiding subharmonic instability. ? the adjustable soft-start circuitry to limit an inrush current during the start-up phase source a current on an external rc network. ? the trans-conductance error amplifier. ? the pulse width modulator and the relative logic circuitry necessary to drive the internal power switches. ? the drivers for embedded high-side and lo w-side n-channel power mosfet switches. ? the high-side current sensing block. ? the low-side current sense to implement diode emulation. ? a voltage monitor circuitry (uvlo) that checks the input and internal voltages. ? a thermal shutdown block, to prevent a thermal runaway. figure 3. block diagram logic hs drv ls drv pfm scp ovp pg dmd fsw/2 ref1 ref3 ref1 ref2 ref osc otp inh uvlo int reg bg ref4 en_ss reg vsum ref5 sw bst vinsw vina comp en_ss fb pg gnda gndp
docid025723 rev 3 9/29 ST1S50 functional description 29 5.1 programmable soft-start and enable the soft-start is essential to assure a correct and safe startup of the step-down converter. it avoids an inrush current surge and makes the output voltage increases monothonically. the soft-start is performed by ramping the non-inverting input (v ref ) of the error amplifier from 0 v to 0.8 v. the ramp of the reference voltage can be programmed selecting the soft- start capacitor that is connected between the en_ss pin and ground. the device sources 5 ? a (typical) in the rc network, ramping the en_ss pin logarithmically from 0.34 v to 1.7 v. the reference of the er ror amplifier ramps, starting when the en_ss pin voltage is equal to 0.7 v (typ.), up from 0 v to 0.8 v accordingly. once the soft-start time ends, the en_ss pin is internally tied to 3. 3 v to avoid injecting noise. 5.2 error amplifier and control loop stability the error amplifier compares the fb pin volt age with the internal 0.8 v reference and it provides the error signal to be compared with t he output of the current sense circuitry, that is the high-side power mosfet current. comparing the output of the error amplifier and the peak inductor current implements the peak current mode control loop. the error amplifier is a trans-conductance amplifier (ota). the uncompensated characteristics are listed in table 5 . table 5. error amplifier characteristics description value dc gain 95 db gm 250 ? a/v r o 240 m ?
functional description ST1S50 10/29 docid025723 rev 3 in figure 4 is shown the simple small signal model for the peak current mode control loop. figure 4. block diagram of the loop for the small signal analysis three main terms can be identified to obtain the loop transfer function: 1. from control (output of e/a) to output, g co (s). 2. from output ( v out ) to fb pin, g div (s). 3. from fb pin to control (output of e/a), g ea (s). the transfer function from control to output g co (s) results: equation 1 where r load represents load resistance, r i the equivalent sensing resistor of the current sense circuitry, ? p the single pole introduced by the lc filter and ? z the zero given by the esr of the output capacitor. f h (s) accounts the sampling effect performed by the pwm comparator on the output of the error amplifier that introduces a double pole at one half of the switching frequency. equation 2 l cout current sense logic and driver slope com pensation pw m com parator error amp rc cc r1 r2 0.8 v high side switch low side switch g co (s) g div (s) g ea (s) vin v c v out v fb g co s ?? r load r i ----------------- - 1 1 r out t sw ? l --------------------------- - m c 1d ? ?? 0.5 ? ? ?? ? + -------------------------------------------------------------------------------------------- - 1 s ? z ------ + ?? ?? 1 s ? p ------ + ?? ?? --------------------- - f h s ?? ??? = ? z 1 esr c out ? ------------------------------- =
docid025723 rev 3 11/29 ST1S50 functional description 29 equation 3 where: equation 4 s n represents the on time slope of the sensed inductor current, s e the slope of the external ramp (v pp peak-to-peak amplitude) that implements the slope compensation to avoid subharmonic oscillations at a duty cycle over 50%. the sampling effect contribution f h (s) is: equation 5 where: equation 6 and equation 7 the resistor to adjust the output voltage gives the term from the output voltage to the fb pin. g div (s) is: ? p 1 r load c out ? ------------------------------------- - m c 1d ? ?? 0.5 ? ? lc out f sw ?? --------------------------------------------- + = m c 1 s e s n ------ + = s e v pp f sw ? = s n v in v out ? l ----------------------------- - r i ? = ? ? ? ? ? ? ? ? ?? 1 1 s ? n q p ? ------------------ - s 2 ? n 2 ------ ++ ------------------------------------------ - = q p 1 ? m c 1d ? ?? 0.5 ? ? ?? ? ---------------------------------------------------------- = ? n ? f sw ? = g div s ?? r 2 r 1 r 2 + -------------------- =
functional description ST1S50 12/29 docid025723 rev 3 the transfer function from the fb to the comp (output of e/a) introduces the singularities (poles and zeroes) to stabilize the loop. in figure 5 is shown the small signal model of the error amplifier with the internal compensation network. figure 5. small signal model for the error amplifier r c and c c are the compensation network, r o represents output resistance of the error amplifier, co represents the internal low frequency pole of the error amplifier. r c and c c introduce a pole and a zero in the open loop gain. c p does not significantly affect system stability and can be neglected. so g ea (s) results: equation 8 where g ea = g m r o the poles of this transfer function are (if c c >> c 0 + c p ): equation 9 equation 10 whereas the zero is defined as: equation 11 co ro cc rc cp gm*vd v fb v ref vd g ea s ?? g ea0 1s + r c c c ?? ?? ? s 2 r 0 c 0 c p + ?? r c c c sr 0 c c ? r 0 c 0 c p + ?? r c c c ? + ? + ?? 1 + ? + ?? ?? ------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------- = f p lf 1 2 ? r 0 c c ?? ? --------------------------------- - = f p hf 1 2 ? r c c 0 c p + ?? ?? ? ---------------------------------------------------- = f z 1 2 ? r c c c ?? ? --------------------------------- =
docid025723 rev 3 13/29 ST1S50 functional description 29 so closing the loop, the loop gain g loop (s) is: equation 12 to stabilize the loop and then to have the pr oper phase margin (> 45) with th e requested bandwidth, r c and c c can be selected as described in section 6.4 on page 18 . 5.3 overcurrent protection the ST1S50 device implements the pulse-by-pulse overcurrent protection. the peak current is sensed through the high-side power mosfet and when it exceeds the overcurrent threshold the high-side is immediately turned off and the low-side conducts the inductor current for the rest of the clock period. during overload condition, since the duty cycle is not set by the control loop but it is limited by the overcurrent threshold, the output voltage drops out of regulation. if the fb falls below 0.734 v the switching frequency is divided by two to keep the inductor current limited around the i lim value. the overload condition is allowed for 256 cont inuous clock cycles. in case the overload condition persists for longer than 257 clock cy cles, the hiccup protection is triggered: the device realizes a soft-start cycle and then, if the overcurrent protec tion is still triggered, stops switching activities and remains disabled for the hiccup times. then it restarts with a soft-start cycle. figure 6. hiccup behavior with persistent short-circuit the hiccup time depends on the selected value of the soft-start capacitor, considering r ss = 4.7 m ? fixed value (see section 6.5 on page 19 ). equation 13 if the feedback falls below 0.3 v before the 256 clock cycle, as a symptom of a short-circuit, the hiccup protection is triggered and the converter reacts as described above in this section. g loop s ?? g co s ?? g div s ?? g ea s ?? ?? = soft-start duration hiccup duration t hiccup s ?? c ss f ?? 2853934 ? =
functional description ST1S50 14/29 docid025723 rev 3 the hiccup is disabled during the startup to allow the v out to start up properly in case of a big output capacitor requiring a high extra current to be charged. 5.4 power good function the pg pin output is an open drain mosfet. the pg is pulled low when the fb pin voltage is lower than 91% of the nominal internal reference (0.8 v). the pg pin is v in compatible. 5.5 hysteretic thermal shutdown the thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 o c. once the junction temperature goes back to about 130 o c, the device restarts in normal operation.
docid025723 rev 3 15/29 ST1S50 application information 29 6 application information 6.1 input capacitor selection the capacitor connected to the input has to be capable to support the maximum input operating voltage and the maximum rms input current required by the device. the input capacitor is subject to a pulsed current, the rm s value of which is dissipated over its esr, affecting the overa ll system efficiency. so the input capacitor must have an rms current rating higher than the maximum rms input current and an esr value compliant with the expected efficiency. the maximum rms input current flowing through the capacitor can be calculated as: equation 14 where i o is the maximum dc output current, d is the duty cycle, ? ? is the efficiency. considering ????? , this function has a maximum at d = 0.5 and it is equal to i o /2. the peak-to-peak voltage across the input capacitor can be calculated as: equation 15 where esr is equivalent series resistance of the capacitor. given the physical dimension, ceramic capaci tors can meet well the requirements of the input filter sustaining a higher input rms curren t than electrolytic / tantalum types. in this case the equation of c in as a function of the target peak-to-peak voltage ripple (v pp ) can be written as follows: equation 16 neglecting the small esr of ceramic capacitors. considering ?? = 1, this function has its maximum in d = 0.5, thus, given the maximum peak- to-peak input voltage (v pp_max ), the minimum input capacitor (c in_min ) value is: equation 17 typically c in is dimensioned to keep the maximum peak-to-peak voltage ripple in the order of 1% of v inmax . i rms i o d 2d 2 ? ? -------------- - ? d 2 ? 2 ------ - + ? = v pp i o c in f sw ? ------------------------- 1 d ? --- - ? ?? ?? d d ? --- - 1d ? ?? ? + ? esr i o ? + ? = c in i o v pp f sw ? -------------------------- - 1 d ? --- - ? ?? ?? d d ? --- - 1d ? ?? ? + ? ? = c in_min i o 2v pp_max f sw ?? ----------------------------------------------- - =
application information ST1S50 16/29 docid025723 rev 3 in table 6 some multi-layer ceramic capacitors suitable for this device are reported. a ceramic bypass capacitor, as clos e as possible to the vina pin, so that additional parasitic esr and esl are minimized, is suggested in order to prevent inst ability on the output voltage due to noise. the value of the bypass capacitor can go from 330 nf to 1 ? f. 6.2 inductor selection the inductance value fixes the current ripple flowing through the output capacitor. so the minimum inductance value to have the expected current ripple has to be selected. the rule to fix the current ripp le value is to have a ripple at 20% - 40% of the output current. in the continuous current mode (ccm), th e inductance value can be calculated by equation 18 : equation 18 where t on is the conduction time of the high-side switch and t off is the conduction time of the low-side switch (in ccm, f sw = 1 / (t on + t off )). the maximum current ripple, given the v out , is obtained at maximum t off , that is at a minimum duty cycle (see section 6.1 to calculate minimum duty). so fixing ? i l = 20% to 30% of the maximum output current, the minimum inductance value can be calculated: equation 19 where f swmin is the minimum switching frequency, according to table 4 on page 6 . the peak current through the inductor is given by: equation 20 so if the inductor value decreases, the peak current (that has to be lower than the current limit of the device) increases. the higher is the inductor value, the higher is the average output current that can be delivered , without reaching the current limit. table 6. input mlcc capacitors manufacturer series cap value ( ? f) rated voltage (v) murata grm31 10 25 grm55 10 25 tdk c3225 10 25 ? i l v in v out ? l ----------------------------- - t on ? v out l -------------- t off ? == l min v out ? i max ---------------- 1d min ? f swmin ---------------------- - ? = i lpk ? i o ? i l 2 -------- + =
docid025723 rev 3 17/29 ST1S50 application information 29 in table 7 some inductor part numbers are listed. 6.3 output capacitor selection the current in the output capacitor has a triangular waveform which generates a voltage ripple across it. this ripple is due to the ca pacitive component (charge or discharge of the output capacitor) and the resistive component ( due to the voltage drop across its esr). so the output capacitor has to be selected in order to have a voltage ripple compliant with the application requirements. the amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection. equation 21 for a ceramic (mlcc) capacitor the capacitive component of the ripple dominates the resistive one. whilst for an electrolyt hic capacitor the opposite is true. since the compensation network is internal, the output capacitor should be selected in order to have a proper phase margin and then a stable control loop. the equations of section 5.2 on page 9 will help to check loop stability given the application conditions, the value of the inductor and of the output capacitor. in table 8 some capacitor series are listed. table 7. inductors manufacturer series inductor value ( ? h) saturation current (a) coilcraft xpl7030 2.2 to 4.7 6.8 to 10.5 xal40xx, 50xx, 60xx 1.5 to 6.8 > 5 wrth we-hc/hca 3.3 to 4.7 7 to 11 we-tpc typ xlh 3.6 to 6.2 4.5 to 6.4 we-pd type l 10 5.6 tdk rlf7030t 2.2 to 4.7 4 to 6 table 8. output capacitors manufacturer series cap value ( ? f) rated voltage (v) esr (m ? ) murata grm32 22 to 100 6.3 to 25 < 5 grm31 10 to 47 6.3 to 25 < 5 panasonic ecj 10 to 22 6.3 < 5 eefcd 10 to 68 6.3 15 to 55 sanyo tpa/b/c 100 to 470 4 to 16 40 to 80 tdk c3225 22 to 100 6.3 < 5 ? v out esr ? i max ? ? i max 8c out f sw ?? ------------------------------------ - + =
application information ST1S50 18/29 docid025723 rev 3 6.4 compensation network selection the compensation network must be chosen to have a phase margin higher than 45 given the application condition (v in , v out , l, c out ) and the requested bandwidth. the larger is the bandwidth, the faster is the loop response to the load transient. maximum allowed bandwidth is one fourth/fifth of the switching frequency (that is 100 - 120 khz). figure 7. compensation network starting from the target bandwidth (f bw ) the compensation network values can be calculated to have a stable loop response basing equation 22 and equation 23 . given the target bandwidth f bw , the resistor r c results: equation 22 where c out is the output capacitor (actual value pr operly derated according to the applied dc voltage), r i is the equivalent sensing resistor of the current sense circuitry (0.3 v/a), gm is the error amplifier trans-conductance (250 ? s) and v ref is the internal reference, 0.8 v. the capacitor c c has to be designed to place the ze ro of the compensation network (f z ) at the frequency of the power stage pole (f p ?? 1 / (2 ? r load c out )). equation 23 the capacitor c p is optional and it can be used to cancel the zero from the esr of the output capacitor. the capacitor c f can be used to have phase boost adding a further zero close to the crossover frequency. c f inserts also a pole at very high frequency, usually negligible. the phase boost effect decreases as the v out decreases. v ref e/a r c c c c p optional c f optional r 1 r 2 v out r c 2 ? f bw v out c out r i ?? ? ? g m v ref ? --------------------------------------------------------------------- - = c c r load c ? out r c ------------------------------------- - =
docid025723 rev 3 19/29 ST1S50 application information 29 6.5 soft-start capacitor selection 6.5.1 reset time the soft-start capacitor allows managing the co rrect rising of the output voltage to prevent a high inrush current. moreover it introduces a reset time in case the device is disabled and re-enabled through uvlo. the re-enable through uvlo, after disable though uvlo, must happen after a certain reset time to assure the proper startup. this reset time is a function of the soft-start capacitor. a 4.7 m ? resistor value in parallel to the soft-s tart capacitor is strongly recommended in order to predict the reset time. figure 8. soft-start circuit the reset time is so calculated: equation 24 figure 9. reset time & 66 (1b66 $0 t reset c ss 4.7m ? 1.97 ?? =
application information ST1S50 20/29 docid025723 rev 3 6.5.2 c ss value when the en_ss pin is tied to ground the device is disabled. when the en_ss is released a current is a source in the soft-start capacitor connected to the pin. no minimum soft-start time is assured in case of no capacitor connected. the fb voltage starts to rise when the en/ss voltage is equal to 0.7 v (typ.), start threshold, and reaches the v ref voltage when the en/ss voltage is equal to 1.5 v (typ.), stop threshold. considering the 4.7 m ? resistor value (see section 6.5.1 ), the soft-start capacitor can be determined by: equation 25 where t ss is the target soft-start time. a delay can be observed from en_ss release and the real v out rising since the en_ss voltage needs to ramp from zero to the enable threshold (340 mv) with a pull-up current of 350 na. the delay results: equation 26 6.6 thermal dissipation the thermal design is important to prevent the thermal shutdown of the device if junction temperature goes above 150 c. the three differ ent sources of losses within the device are: a) conduction losses due to on resistance of the high-side switch (r hs ) and low-side switch (r ls ); these are equal to: equation 27 where d is the duty cycle of the application. note th at the duty cycle is theoretically given by the ratio between the v out and v in , but actually it is slightly higher to compensate the losses of the regulator. b) switching losses due to the high-si de power mosfet turn on and off; these can be calculated as: equation 28 where t rise and t fall are the overlap times of the voltage across the high-side power switch (v ds ) and the current flowing into it during turn on and turn off phases, as shown in figure 10 . t sw is the equivalent switching time. for this device the typical value for the equivalent switching time is 20 ns. c ss f ?? t ss s ?? 154873 ------------------- - = t delay 0.340v c ? ss 350na ---------------------------------- - = p cond r hs i out 2 dr ls i out 2 1d ? ?? ?? + ?? = p sw v in i out t rise t fall + ?? 2 ------------------------------------------ - fsw ?? ? v in i out t sw f sw ??? ==
docid025723 rev 3 21/29 ST1S50 application information 29 c) quiescent current lo sses, calculated as: equation 29 where i q is the quiescent current (i q = 500 ? a maximum). the junction temperature t j can be calculated as: equation 30 where t a is the ambient temperature and p tot is the sum of the power losses just seen. r thja is equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conducti on from the junction to the ambient. for this device the path through the exposed pad is the one conducting the largest amount of heat. the r thja measured on the demonstration board described in section 6.7 is about 60 c/w for the vfdfpn8 package. figure 10. switching losses 6.7 layout consideration the pc board layout of the switching dc/dc r egulator is very import ant to minimize the noise injected in high impedance nodes, to reduce interferences generated by the high switching current loops and to optim ize the reliability of the device. in order to avoid emc problems, the high switching current loops have to be as short as possible. in the buck converter two are the high switching current loops: during the on-time, the pulsed current flows through the input capaci tor, the high-side power switch, the inductor and the output capacitor; during the off-time, through the low-side power switch, the inductor and the output capacitor. p q v in i q ? = t j t a rth ja p tot ? + = v sw i sw,hs v in v ds,hs p cond,hs p cond,ls p sw t fall t rise
application information ST1S50 22/29 docid025723 rev 3 an input capacitor connected to vinsw has to be placed as close as possible to the device, to avoid spikes on vinsw due to the st ray inductance and the pulsed input current. in order to prevent dynamic unbalance between vinsw and vina, the trace connecting the vina pin to the input must be derived from vinsw. the feedback pin (fb) connected to an external resistor divider is a high impedance node. the interferences can be minimized by routing the feedback node with a very short trace and as far away as possible from high current paths a single point connection from signal gr ound to power ground is suggested. thanks to the exposed pad of the device, the ground plane helps to reduce thermal resistance junction to ambient; so a large gr ound plane, soldered to the exposed pad, enhances the thermal performance of the converter allowing high power conversion. figure 11. pcb layout gndp vinsw vina gnda fb sw bst pg en_ss comp ST1S50pur 1 2 3 4 5 10 9 8 7 6 cout cin_p cin_a r1 r2 rc cc css cbst l ground plane v out v in gnd
docid025723 rev 3 23/29 ST1S50 application information 29 6.8 demonstration board figure 12. demonstration board schematic & 10 5 5 73 3*22' 5 n & s & s 73 9287 73 *1' 73 *1' 5 0hj 8 676 3*22' (1b66 9,1b6: )% 3*1' /; 6*1' %227 (3 9,1b$ &203 73 9,1 73 (1b6666 & 10 & x) 5 n 5 n & 10 / x+ & q & x) & x) 5 10 5 0 - $09 table 9. component list reference part number de scription manufacturer u1 ST1S50pur stmicroelectronics ? l1 xal6060-472mec 4.7 ? h, isat = 10.5 a, irms = 8 a coilcraft c1 optional c2 100 nf, 25 v c3 grm31cr61e106ka12l 10 ? f, 25 v, x5r, 1206 murata c4 grm21br71e225ka73l 2.2 ? f, 25 v, x7r, 0805 murata c5 22 nf, 50 v, 0603 c6 470 pf, 50 v, 0603 c7 10 pf, 50 v, 0603 c8 grm32er61e226ke15l 22 ? f, 25 v, x5r, 1210 murata r1 16 k ?? 1%, 0.1 w, 0603 r2 5.1 k ?? 1%, 0.1 w, 0603 r3 n.m. r4 1 m ?? 1%, 0.1 w, 0603 r5 10 ?? 1%, 0.1 w, 0603 r6 68 k ?? 1%, 0.1 w, 0603 r7 4.7 m ?? 1%, 0.1 w, 0603
typical characteristics ST1S50 24/29 docid025723 rev 3 7 typical characteristics figure 13. efficiency vs. i out - v in = 12 v figure 14. efficiency vs. i out - v in = 5 v 20 30 40 50 60 70 80 90 100 0.000 0.500 1.000 1.500 2.000 2.500 3.000 3.500 4.000 4.500 efficiency ? [%] iout ? [a] vin=12v vo=1.2v vo=3.3v vo=5v 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 efficiency ? [%] iout ? [a] vin=5v vo=3.3v figure 15. start-up releasing en_ss pin figure 16. long overload condition figure 17. quick overload figure 18. start-up with shorted v out sw 2v/div vout 0.5v/div ss 1v/div il 1a/div 50us/div 2us/div v in =12v, v out =3.3v, quick overcurrent v fb falls below 0.3v
docid025723 rev 3 25/29 ST1S50 typical characteristics 29 figure 19. reset time
package information ST1S50 26/29 docid025723 rev 3 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com . ecopack is an st trademark. figure 20. vfdfpn8 (3 x 3 x 1 mm) package outline (bottom view) 9)')31
docid025723 rev 3 27/29 ST1S50 package information 29 table 10. vfdfpn8 (3 x 3 x 1 mm) package mechanical data symbol dimensions ( mm ) min. typ. max. a 0.80 0.90 1.00 a1 0.02 0.05 a3 0.20 b 0.18 0.25 0.30 d3.00 d2 2.234 2.384 2.484 e3.00 e2 1.496 1.646 1.746 e0.50 l 0.30 0.40 0.50 ddd 0.05
order code ST1S50 28/29 docid025723 rev 3 9 order code 10 revision history table 11. ordering information order code package packing ST1S50pur vfdfpn8 3 x 3 x 1 mm - 10l tape and reel table 12. document revision history date revision changes 18-dec-2013 1 initial release. 24-feb-2014 2 replaced label ?preliminary data? by ?production data? on page 1. 01-jul-2014 3 updated table 1: pin description on page 4 (updated ?description? of pins: 1 gndp and 4 gnda). updated figure 12 (replaced by new figure). updated table 11 (added ?packing? column).
docid025723 rev 3 29/29 ST1S50 29 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of ST1S50

	To Download ST1S50 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .